High-power circuits have voltage or current an order of magnitude higher than low-power circuits. A high-power circuit is a system, not a single component — it must be designed with consideration for the circuit board, electronic devices, thermal management and power supply together.

Designers must ensure the circuit operates at the proper voltage and current and has sufficient cooling and safety provisions.

• Signal integrity — electrical signals must travel traces free from noise and interference; follow best-practice layout and routing.
• EMI/EMC compliance — interference affects the device itself and other nearby systems.
• Power consumption — portability and battery operation may demand very low power; layout and materials must support efficiency.
• DfM (Design for Manufacturability) — medical boards typically require IPC 6012 Class 3, so design and supplier must be compatible with the strictest aspects of the design.
• High reliability — failure can put lives at risk. Parts must withstand the intended environment (temperature, humidity).
• Quality control — closely monitored manufacturing ensures PCBs meet required tolerances, dimensions and electrical properties.
• Traceability — every component including the PCB must be traceable from supplier to finished product. Maintain comprehensive documentation: material traceability, test results, validation reports.
• Material selection — compatible with device use, sterilisation method and regulatory requirements. UL-approved where appropriate, and free from contaminants.
• Environmental controls — manufacturing in a clean, controlled environment.
• Testing & validation — electrical, environmental, and component compatibility must all be verified.

• Specific architecture requirements to comply with SIL (Safety Integrity Level).
• Methodology for obtaining FCC compliance (does not consider the concept of fail-safe).

The three fundamental principles:

• Zero risk “can never be achieved”.
• Non-tolerable risks must be reduced.
• Security management must be considered from the beginning.

IEC 61508 underpins further railway standards such as CENELEC.

The common European standard is UNE-EN 50124-1. Because of the high reliability required, IEC 61508 — an international standard for functional safety of electrical/electronic/programmable electronic systems — is also fundamental.

• Your supplier should have its own PCB specification. PCB Connect’s spec addresses IPC AABUS (As Agreed Upon Between User and Supplier) rules and, in some cases, exceeds IPC class 2 for high reliability at the best possible price.
• Select high-quality materials — essential for the reliability and durability aerospace demands.
• Conformal coating is common on assembled aerospace PCBs to protect against environmental factors and prevent corrosion. Excellent adhesion to the soldermask is required — PCB Connect has tested and certified soldermask/conformal-coating combinations that secure sufficient adhesion.
• Aerospace regulations are extensive and evolving — work with a trusted PCB supplier from the start of the design phase.

Suppliers for aerospace must meet AS9100, which imposes additional measures on top of ISO 9000 international quality requirements — an extra layer of protection for everyone involved.

EV charging is a high-power application — significantly greater voltage/current than low-power circuits. Designers must ensure the circuit works within proper voltage and current parameters while incorporating adequate cooling and safety.

High-power PCBs typically follow one of two approaches: layout design (arrangement of components on the PCB) or reference design (layouts built around specific references). The layout must be carefully crafted to accommodate high-power components and minimise noise.

Component placement is a key technique for reducing thermal resistance when high-power components are on the PCB.

Design in more mounting holes — more mounting points means more stability and more places for dampening devices.

Stackup matters: for extreme shock or vibration, the prepreg needs enough resin content to withstand flex and stress on connection points. Consider prepregs with over 50% resin content, and more than two sheets for additional bonding strength. But don’t overdo it — too much prepreg harms layer-to-layer registration, so three sheets is a sensible upper bound unless your supplier says otherwise.

If you need more thickness but can’t add more prepreg, use unclad cores. They are already cured and don’t add resin to the press cycle, so registration is preserved.

• Placement check
• Test pin
• Component packaging
• Mechanical check
• Technical check
• Constraint rules
• Routing check
• Timing design
• Power design check
• DRC check
• Silkscreen check
• Gerber review

• Annular ring issues.
• Plated through hole (PTH) to copper.
• Non-plated through hole (NPTH) / NPTH slots to copper.
• Holes located on edge of an SMD pad, or very close to SMD.
• Trace width and isolation spacing don’t work with the selected base copper foil thickness.
• Stubs (unterminated traces) on copper layer.
• Slivers and same-net spacing in copper layers.
• Copper to edge — distance between copper features and the profile.
• Improper SMD/BGA pad design.
• Soldermask oversized / lacking oversize in the same design.
• Soldermask bridge / web too small.
• Coverage of soldermask.
• Legend print problems.

Design guidelines are available for:

• Multilayer PCB
• Flex / Rigid-Flex PCB
• Stackups and Impedances
• Copper Coin
• HDI PCB
• Ultra HDI PCB
• Semi-Flex PCB

Cost drivers fall into two categories. Hard cost drivers relate to the physical PCB itself — their impact on cost and sustainability is tangible. Soft cost drivers are less visible; unaddressed, they lead to engineering delays, lost time and mis-specified demands that drive cost up or fail to deliver quality/reliability.

Yes — significantly. Size, batch quantity, material choice, layer count and specifications/tolerances all influence price. 80–90% of the cost is built into the product during the early design stages, and many cost drivers also impact sustainability. Early decisions matter doubly.

As early as possible. Getting it right at the design stage can make all the difference between a PCB that meets expectations and one that doesn’t — and that’s not always about being faulty. Acceptance or rejection criteria depend on the standards used to evaluate them.

PCB Connect views design support not only as defining what’s needed, but also as what we do with your design from receipt of data through to the finished product.

You can find our capabilities for Rigid, Flex Rigid, HDI and Flexible PCBs here in the following link:

When you fill in the specifications in your RFQ, you should specify:

• Layer Count
• Surface Treatment
• Board Size
• Panel Size
• Boards/Pni
• Material
• Board Thickness
• Solder Mask Color
• Legend Print
• Production Specification
• Other important specification, if it’s needed.

Tenting in PCB means covering the annular ring via a hole with a solder mask. Tented Vias are those that are completely covered with a solder mask.

Via tenting is performed to reduce the number of exposed conductive pads on a PCB.This mitigates the probability of physical damage like corrosion and shorts happening due to solder bridging.

Materials are different. Tented Vias use dry film solder mask, Plugging Vias use liquid solder mask or resin. Also, Plugging Vias allows partial material penetrate into the via, but Tented Vias just need to bridge over vias wherein no additional materials are in the hole.

FR4 is the most common material grade that used for fabricated circuit boards. ‘FR’ indicates the material is flame retardant and the ‘4’ indicates woven glass reinforced epoxy resin

CEM-1 is low-cost, flame-retardant, cellulose-paper-based laminate with only one layer of woven glass fabric.

CEM-2 has cellulose paper core and woven glass fabric surface.

CEM-3 is very similar to the most commonly used PCB material, FR-4.

IPC 4101E define thermal conductivity level for aluminum PCB as below:

Level A ≤1.0

Level B >1.0 ≤2.0

Level C >2.0 ≤3.0

Level D >3.0 ≤5.0

Level X AABUS

The “peelable solder mask” it’s a liquid and (also known as strippable mask or blue-mask) is applied by screen-printing, act as in-process protection and are removed after processing at the assembler.

It provides printed circuit boards with protection in soldering processes like wave soldering, selective soldering or at the PCB level a surface finish protection.

Initial copper means base copper which come from the laminate we buy. Final copper means the copper thickness for the finished PCB , it include base copper and plating copper.

Yes, our factory comply with RoHS Directive.

RoHS stands for Restriction of Certain Hazardous Substances. It is an European legislation that bans six hazardous substances from manufacturing processes: cadmium (Cd), mercury (Hg), hexavalent chromium (Cr (VI)), polybrominated biphenyls (PBBs), polybrominated diphenyl ethers (PBDEs) and lead (Pb).

PCB shelf life were defined based on PCB surface finishes, IPC define PCB shelf life as below:

HASL – 12 months

HASL lead free – 12 months

ENIG – 12months

ENEPIG – 12months

Immersion Silver – 6 months

Immersion Tin – 6 months

OSP – 6 months

Mouse bite holes are designed in panel for facilitating separate PCB from frame, it is normally design in two rows.

V-cut is also called V-Scoring, it is used for mechanical pre-separation of circuit boards.

V-cut can only be performed along straight line, A V-shaped breaking line is formed in the circuit board with a precision cutting tool.

Performing V-cut is just for PCB separation become easily.

FR4 is the most popular type of material in the PCB manufacturing. FR4 material is ideal to produce one layer PCB or multilayer PCB. It suits for demands for flexible or rigid PCBs as well.

Multilayer PCB is a printed circuit board that has more than, at least, four layers, with one or multiple conductor patterns inside the board.

The HDI – High Density Interconnector PCBs have a higher wiring density compared with standard PCBs.

Flexible printed circuit boards are boards that uses flexible based material in your applications. They can be single or double sided up to 6 layers.

• Use the same hole size for all holes in the coin.
• When different coin sizes are used on one unit, the difference should be ≥1 mm. If <1 mm, use the same size.
• Minimum difference between long and short sides of a coin: ≥1.0 mm. A difference <0.3 mm is treated as the same size.
• Up to 32 coins per unit may be possible — confirm with PCB Connect.
• V5 connections: laser milling + copper filling. Preferred max opening to fill: 4×4 mm.
• Attachment: embedded, press-fit, or conductive adhesive film.
• Usable in high layer count, IPC-4761 type VII plugging, HDI, rigid-flex — factory limitations apply.
• Fewer than 3 different coin types/sizes per unit recommended.
• Blind via in a coin: aspect ratio limit <1:1, optimal 0.8:1.
• Any coin construction must be symmetric — same core & prepreg each side of the centre core.
• T-coin shape must be symmetrical in X and Y (Qx, Qy can differ but Q same both sides).
• Conductive adhesive attachment depends on design & factory — check with PCB Connect.
• Press-fit push/pull strength may be limited — confirm with PCB Connect.

A copper coin is a piece of solid copper inserted onto or into the PCB, typically under components that need cooling. It can provide up to 10× the cooling of a via farm of the same size.

• Above 2 GHz with critical timing: consider medium/high/ultra-high-speed materials and flat glass styles.
• Ensure reliable lamination — let the factory pick prepreg count, styles and resin content to avoid resin starvation.
• Primary drivers of signal loss:
• Line length — losses are directly proportional.
• Dielectric loss — reduce with material selection.
• Copper loss — cross-section area (stackup design).
• Surface roughness — reduce via material / stackup choice.
• Tighter tolerances (< ±10%): discuss with PCB Connect.
• Rigid-flex: separate calculations for rigid and flex parts of the same signal.
• Solder mask thickness & dielectric constant adjusted by manufacturer based on their process.
• Resin-% differences affect impedance.

• Above 2 GHz with critical timing: consider medium/high/ultra-high-speed materials and flat glass styles.
• Ensure reliable lamination — let the factory pick prepreg count, styles and resin content to avoid resin starvation.
• Primary drivers of signal loss:
• Line length — losses are directly proportional.
• Dielectric loss — reduce with material selection.
• Copper loss — cross-section area (stackup design).
• Surface roughness — reduce via material / stackup choice.
• Tighter tolerances (< ±10%): discuss with PCB Connect.
• Rigid-flex: separate calculations for rigid and flex parts of the same signal.
• Solder mask thickness & dielectric constant adjusted by manufacturer based on their process.
• Resin-% differences affect impedance.

• Make the stackup symmetric.
• Foil build normally suggested; special core builds (e.g. Rogers) are possible but not common.
• Thickness tolerance: ±10% for >1 mm boards, ±0.1 mm for 1 mm boards. ≤1 mm boards: approved by PCB Connect.
• Minimum dielectric thickness: 90 µm per IPC if the fab drawing doesn’t specify and there are no microvias.
• Use a maximum of 3 sheets of prepreg to bond layers.
• Production stackup may differ slightly from specified — an EQ will confirm (due to copper distribution, stocks, etc).
• Thicker copper foils need thicker dielectric between layers.
• Foil thickness after processing ≠ base foil.
• Resin-% differences in the same prepreg type affect thickness.
• For microvias, consider aspect ratio: 0.8:1 recommended, 1:1 advanced.

• Make the stackup symmetric.
• Foil build normally suggested; special core builds (e.g. Rogers) are possible but not common.
• Thickness tolerance: ±10% for >1 mm boards, ±0.1 mm for 1 mm boards. ≤1 mm boards: approved by PCB Connect.
• Minimum dielectric thickness: 90 µm per IPC if the fab drawing doesn’t specify and there are no microvias.
• Use a maximum of 3 sheets of prepreg to bond layers.
• Production stackup may differ slightly from specified — an EQ will confirm (due to copper distribution, stocks, etc).
• Thicker copper foils need thicker dielectric between layers.
• Foil thickness after processing ≠ base foil.
• Resin-% differences in the same prepreg type affect thickness.
• For microvias, consider aspect ratio: 0.8:1 recommended, 1:1 advanced.

Ultra HDI is defined by IPC as a PCB with attributes beyond IPC-2226 A producibility level C, where one or more layers have lines or spaces below 50 µm. PCB Connect classifies factories along this ladder because of different production technologies and equipment needs.

• Reduce track before space when smaller size is needed.
• Every stackup must be approved case by case, especially coreless or odd-layer designs.
• Minimum core/prepreg dielectric thickness: 0.025 mm (1 mil).
• Overall board thickness: 0.12–2.0 mm (≤ 2.0 mm).
• Avoid plated through holes when start/stop layers are UHDI.
• UHDI copper is thinner than normal HDI. Minimum final conductor copper is typically 8–30 µm.
• Cores with micro-via drilling available on request (core thickness 60–160 µm, hole size ≤ 80 µm).
• Bonding pad width measured at pad top; min bonding pad area must be specified & agreed.
• Pad-size tolerance: ± 10 µm standard; advanced capability ± 5 µm.
• Solder mask flatness 5–7 µm → dry film solder mask (limited to substrate-like factories).
• Track/gap < 35 µm: evaluated case by case, typically with limited layer count.
• Surface treatments available: ENIG, ENEPIG, OSP, Immersion Tin, soft gold. For FCBGA, ENEPIG recommended.

• Use a thin FR4 core 0.075–0.1 mm — smoother surface and better thickness tolerance. Only 1L copper recommended.
• Use a bending die (mandrel) that fully supports the semi-flex area during bending.
• Copper-fill the bending area for reliability — add dummy copper where needed, in cooperation with the PCB Connect technical team.
• Bend in the warp direction of the glass fibre and keep all bending zones in the same direction.
• Maximum bending cycles must be discussed with PCB Connect and stated in the procurement documentation.
• Flexible soldermask is generally OK for <10 bending cycles and low bending strength; for more cycles or high flexural strength, use coverlay.
• Bending area must face outwards. Facing inwards greatly increases stress. Copper must be on the outer layer in the bend area.
• Single-copper-layer bend area: add copper fill to even out distribution and minimise cracks.

G = (π × R × A₂ ÷ 180) + 4 mm

G = minimum bend length

R = basic inner bend radius

A₂ = bending angle in degrees

4 mm = empirical safety compensation

Semi-flex is effectively a standard multilayer PCB built with specific FR4, depth-controlled so the thinner area provides a flexing section.

Use for flex-to-install static applications or applications with a very limited / controlled number of bends. Dynamic use or multiple flexing increases the risk of cracks in FR4/copper.

• Use adhesiveless polyimide systems — better reliability and lower z-axis CTE (acrylic = 2.5× PI in z-axis CTE).
• For dynamic applications, keep layer count as low as possible.
• Static / flex-to-install can support higher layer counts in the flex construction.
• Semi-flex can be used for flex-to-install; multiple flexing risks cracks in FR4/copper.
• For dynamic use, choose FPC + coverlay with similar properties.
• Use IPC-2223 to calculate flex length for minimum bend radius.
• Flex length approximations: 1L = 3–6× FPC thickness; 2L = 7–10×; Dynamic = 20–40×.
• No sharp edges or corners on flex outline or circuitry.
• Solid copper fill on back of gold fingers if stiffeners can’t be added.
• Always keep stiffeners the same thickness.
• Design pads larger than coverlay.
• No overlay of tracks for dynamic applications — offset L1 vs L2.
• IPC allows 300 µm adhesive squeeze-out from coverlay edge — maintain spacing.

Demand is rising across all segments, with especially strong demand from medical, defence and industrial markets — driven by space, weight and mechanical routing constraints.

• Aspect ratio for laser-drilled microvia (L1–L2): 0.8:1 standard, 1:1 advanced.
• For reliability, microvia should be 100 µm when copper filled.
• Entry and capture pads should be 200 µm greater than the microvia size.
• Epoxy-plugged via holes should be the same size — no more than 0.15 mm variation.
• Always copper-fill microvia in SMD pad. More costly, but far more reliable.
• Stagger (don’t stack) microvias on buried via holes — relieves stress.
• Space between microvia holes: 400 µm recommended, 300 µm minimum.
• Plug through-hole via in SMD pad per IPC-4761 type VII.
• Skip via structures are not preferred — staggered is recommended.
• Always resin-fill skip via holes.
• Aspect ratio for skip microvia (L1–L3): 0.67:1 standard, 0.8:1 advanced.

IPC-2226 defines HDI as a PCB with higher wiring density per unit area than conventional circuit boards.

• Aim for a symmetrical stack-up in dielectric spacing to reduce bow & twist.
• Place internal copper plane layers symmetrically in the stack-up.
• Avoid cores as outer layers — this increases cost.
• Use the same copper thickness on both sides of an inner layer core.
• Balance top/bottom copper area using copper filling in empty areas to avoid over/under plating.
• Avoid tight hole tolerances when they’re not needed.
• Allow the factory to remove non-functional via pads if uncritical (see IPC-2222B, 9.1.4 table 9-3).
• Use tear-drops in all layers, on all designs, for both IPC class 2 and 3.
• Use balanced component spacing to avoid uneven copper and inconsistent heat dissipation.
• Use back-drilling instead of sequential lamination to avoid via stubs — saves cost.
• Use thin trace widths only locally (e.g. inside BGA patterns).
• Prioritise trace separation before trace width to leave room for etch compensation.

A Multilayer PCB is built with three or more conductive copper layers. The inner layers are processed in pairs on a core and then bonded together using prepreg as the insulating layer.

Both sides of the board can be used to mount components, and vias provide the electrical connections between the different layers.